Article ID: 000081088 Content Type: Troubleshooting Last Reviewed: 09/23/2015

Arria V and Arria V SoC Core-to-Periphery (C2P) Timing Miscorrelation

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    There is a timing model miscorrelation in a subset of Core-to-Periphery (C2P) data paths which might result in an incorrect FPGA output for designs that have low setup slack in the affected paths.

    This affects Arria® V and Arria V SoC designs (excluding Arria V GZ devices) using the affected output pins in the top and/or bottom I/O banks.

    This issue does not affect Periphery-to-Core (P2C) transfers, I/O banks on the right, transceivers and hard memory controller.

    Resolution

    Checking affected pins used in design
    If your design targets Arria V or Arria V SoC devices (excluding Arria V GZ devices), please refer to the ArriaV_PinList Excel file for a list of affected pins indicated in red text. If your design uses any of the affected pins, rerun timing analysis using the available timing model patch to reflect the actual timing margin in your design as described below.

    Rerun Timing Analysis in the Updated Software Version
    If your designs target Arria V or Arria V SoC devices (excluding Arria V GZ devices), or if you are debugging a timing-related issue, re-run timing analysis using the available timing model patch as follow:

    1. Back up the design database.
    2. Open the design in the earlier Quartus® II software version, and then export the database. On the Project menu, click Export Database. When you are prompted, export the database to the suggested export_db directory.
    3. Start Quartus II software with the installed timing model patch.
    4. Open the project. When you are prompted whether to overwrite the older database version, click \'Yes’, and import the database from the export_db directory.
    5. Run the TimeQuest timing analyzer on the design.
    6. If there are timing violations, recompile with the timing model patch to close timing on the design.

    Steps to Improve Timing Closure (UniPHY Quarter Rate DDR3)
    To improve timing closure in quarter-rate UniPHY DDR3 interfaces on Arria V or Arria V SoC devices, Altera recommends changing the phase of the clock domain immediately preceding the periphery clock domain. Follow these steps to ease timing closure in using the timing model patch.
    1. Create a new text file and name it ‘quartus.ini’
    2. Save this file in your home directory.The below are sample home directories, but can be different on your computer based on your environment variables.
      • For Windows : C:\Users\<username>
      • For Linux : /home/<username>
    3. Insert the following INI command in the quartus.ini file to increase the setup relationship by the specified amount of phase value.
      • uniphy_av_hr_clock_phase = <phase_value>

      The legal <phase_value> to be used are in the decremental fashion of 22.5° from the default value of 360°  (i.e the <phase_value> to be inserted in the quartus.ini file are 337.5°, 315°, 292.5°, 270°, etc).
      For example:
      • Inserting uniphy_av_hr_clock_phase=337.5 will increase the default setup relationship by 22.5°.
      • Inserting uniphy_av_hr_clock_phase=315 will increase the default setup relationship by 45°.
      • Inserting uniphy_av_hr_clock_phase=292.5 will increase the default setup relationship by 67.5°.
      • Inserting uniphy_av_hr_clock_phase=270 will increase the default setup relationship by 90°.
    4. Regenerate the UniPHY IP, recompile the design and ensure timing closure.

    Steps to Improve Timing Closure (LVDS Tx)
    To improve timing closure in LVDS Tx on Arria V or Arria V SoC devices, Altera recommends changing the phase of the clock domain immediately preceding the periphery clock domain. Follow these steps to ease timing closure using the timing model patch*.

    1. Create a new text file and name it ‘quartus.ini’
    2. Save this file in your project directory.
    3. Insert the following INI command in the quartus.ini file to turn on the phase shifting feature. This by default will increase the setup relationship of the transfers by 400ps.
      • av_lvds_c2p_sclk_phase_shift_en = on

    4. Delete the db and incremental_db directories in the project, recompile the design and ensure timing closure.
    5. If timing is not met after using the command above, try using other phase shift values by adding the following command in the same quartus.ini file and repeat step 4.
      • av_lvds_c2p_sclk_phase_shift = <phase_value>

    Note: The phase value is in ps which must not be included in the ini variable.

    To update the timing model, download and install the appropriate the patch for your version of the Quartus II software.

    The timing model update will be included version 15.0 Update 2 of the Quartus II software.

    Related Products

    This article applies to 4 products

    Arria® V GT FPGA
    Arria® V GX FPGA
    Arria® V ST SoC FPGA
    Arria® V SX SoC FPGA

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