input a,b; output o1,o2; reg o2; assign o1 = a&b; always@(posedge clock) o2 = a&b;
To implement this code in only one LE, both outputs must have the same expression on the right hand side of the assignments (like
a&b in this case). Additionally, turn the Registered Packing Option on in the Quartus software for this implementation.
However, if your design uses carry chains, then the number of LEs cannot be minimized this way. See the following code:
input [3:0] a,b; output [3:0] outa,outb; reg outb; assign outa= a b; always@(posedge clock) outb = a b;
Here, the design must use carry chains, and will be implemented in eight LEs and not four.
A future version of the Quartus software may allow register packing and carry chains to be implemented in the same LE.