Article ID: 000081065 Content Type: Troubleshooting Last Reviewed: 01/28/2014

Why does my Configuration via Protocol (CvP) design hang the PCIe bus after a CvP core fabric load?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The PCIe® bus can hang when using the CvP Update with Revision Flow if any partitions that are used for CvP become empty. The choices in the Quartus® II software when creating a partition for CvP Update with Revision Flow are Empty, Source, Post-Fit, and Post-Synthesis. The default is Empty to comply with Partial Reconfiguration requirements.

Resolution

When using CvP Update with Revision Flow, ensure that no CvP partitions use the Empty option. Ensure all partitions specify Source, Post-Fit, or Post-Synthesis based on your system\'s need.

Related Products

This article applies to 13 products

Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Stratix® V GX FPGA
Stratix® V GT FPGA
Cyclone® V GX FPGA
Stratix® V GS FPGA
Arria® V GZ FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GT FPGA
Cyclone® V SE SoC FPGA
Arria® V GX FPGA

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