Critical Issue
The DisplayPort sink general register address 0x0001 (DPRX_RX_STATUS)
corrupts when you configure the RX maximum lane count (RX_MAX_LANE_COUNT) to 2 or
1.
DPRX_RX_STATUS definition:
- Bit16: SYNC_LOSS
- Bit7: SYM_LOCK Lane3
- Bit6: SYM_LOCK Lane2
- Bit5: SYM_LOCK Lane1
- Bit4: SYM_LOCK Lane0
- Bit3: CR_DONE Lane3
- Bit2: CR_DONE Lane2
- Bit1: CR_DONE Lane1
- Bit0: CR_DONE Lane0
However, when you configure the RX maximum lane count to 2 or 1, the register bit definition is shifted.
This issue causes the RX core to fail link training in AUX_GPU mode because the software API fails to detect SYM_LOCK due to the shift in the bits.
To work around this issue, set the software API to detect the shifted
DPRX_RX_STATUS definition:
If RX_MAX_LANE_COUNT = 4 (follow the standard definition)
- Bit16: SYNC_LOSS
- Bit7: SYM_LOCK Lane3
- Bit6: SYM_LOCK Lane2
- Bit5: SYM_LOCK Lane1
- Bit4: SYM_LOCK Lane0
- Bit3: CR_DONE Lane3
- Bit2: CR_DONE Lane2
- Bit1: CR_DONE Lane1
- Bit0: CR_DONE Lane0
If RX_MAX_LANE_COUNT = 2
- Bit12: SYNC_LOSS
- Bit3: SYM_LOCK Lane1
- Bit2: SYM_LOCK Lane0
- Bit1: CR_DONE Lane1
- Bit0: CR_DONE Lane0
If RX_MAX_LANE_COUNT = 1
- Bit10: SYNC_LOSS
- Bit1: SYM_LOCK Lane0
- Bit0: CR_DONE Lane0
This issue is fixed in version 16.0 Update 1 of the DisplayPort IP core.