The Quartus® II software versions 7.0 and earlier may generate this warning message if you use a variable to control a loop in Verilog HDL as in the following example:
if ( !rst_n )
begin
for ( i = 0; i < depth; i = i 1)
mem[i] = {width{1'b0}} ;
end
This problem is fixed beginning with the Quartus II software version 7.1.
In the example above, the Quartus II software versions 7.0 and earlier issue the warning for a temporary loop variable that is not a signal in the final design. In the example, the variable "i" is used for looping, and it is initialized before the beginning of the loop in the Verilog code but it is not used in the rest of the code. The software synthesizes a latch for this temporary variable. In the final design netlist, the latch does not drive logic, so it is removed. However the software issues the inferred latch warning before it removes signals with no fanout.
Unless you refer to the variable outside the always construct, Quartus II software synthesis removes the latch, and you can ignore the warning.