Article ID: 000081031 Content Type: Troubleshooting Last Reviewed: 11/12/2013

Stratix® II GX Device Handbook: Known Issues

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Description

Issue 132933: Volume 2, Chapter 13. Configuring Stratix II and Stratix II GX Devices, Version 4.5

Table 13–22. Dedicated Configuration Pins on the Stratix II and Stratix II GX Device. The table incorrectly states "When using EPC2 devices, only external 10-k. pull-up resistors should be used." in the descriptions for nSTATUS and CONF_DONE. This is for EPC1, not for EPC2. The table should say "When using EPC1 devices, only external 10-k. pull-up resistors should be used." in descriptions for nSTATUS and CONF_DONE.

Issue 1001910, Volume 2, Chapter 11, "High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices", Version 2.3

DPA Usage Guidelines show each fast PLL can drive up to 25 contiguous rows in DPA mode in a single bank (not including the reference clock row). This restriction was intended to ensure minimum skew between any two channels. Starting in the Quartus® II software version 8.0, this restriction has been removed. To account for skew between any two channels (which can also result from board level skew), use receiver data realignment to ensure alignment across multiple channels.

Issue 10003861, Volume 1, Chapter 4 "DC & Switching Characteristics" Version 4.5

Table 4-1 shows the absolute maximum DC voltage (Vi) is 4.6V.  This should be 4.0V.  During AC transitions, the voltage can exceed 4.0V for duty cycles as shown in Table 4-2.

Resolution

Resolved issues:

Issue 10001685, Volume 1, Chapter 4 "DC and Switching Characteristics" Version 4.5

The Rd (differential on chip termination) specification in table 4-50 shows the VCCIO conditions as 3.3V which is incorrect.  The correct VCCIO voltage for the Rd tolerance specification is 2.5V. 

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