Article ID: 000081028 Content Type: Troubleshooting Last Reviewed: 08/10/2015

Documentation Errors for Boot from FPGA Features

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    The documentation for the SoC HPS v.12.1 describes signals for the boot-from-FPGA feature. These signals are not accessible to logic in the FPGA portion of the SoC.

    Resolution

    Update to v14.0 or later of the following documents:

    • The Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual (FPGA Manager and Instantiating the HPS Component chapters)
    • The Arria V Device Handbook Volume 3: Hard Processor System Technical Reference Manual (FPGA Manager and Instantiating the HPS Component chapters)
    • The Cyclone V SoC HPS Address Map and Register Definitions
    • The Arria V SoC HPS Address Map and Register Definitions

    These documents contain corrected descriptions of the f2h_boot_from_fpga_on_failure and f2h_boot_from_fpga_ready signals, indicating that the signals are always pulled high.

    Related Products

    This article applies to 2 products

    Arria® V FPGAs and SoC FPGAs
    Cyclone® V FPGAs and SoC FPGAs

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