Article ID: 000081004 Content Type: Troubleshooting Last Reviewed: 08/27/2013

Is there any issue with the "rx_dpa_locked" signal behavior in Modelsim gate level simulation with Quartus II software version 9.1?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Yes, if you enable the PLL calibration feature in the altlvds MegaWizard™ for Stratix® III devices in Quartus® II software version 9.1, the "rx_dpa_locked" signal may never go to 'high' in Modelsim gate level simulation. This is not representative of actual device behavior.

    Resolution

    This problem is fixed in the Quartus II software version 10.0.

    Related Products

    This article applies to 1 products

    Stratix® III FPGAs

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