Article ID: 000080995 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why do I get timing violations when using the altlvds_tx Megafunction?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

When using the transmitter function of altlvds (altlvds_tx), you may get setup timing violations when using tx_inclock to register the data that feeds the SERDES blocks.  The altlvds_tx Megafunction gives you the choice to register the tx_in data with either the tx_inclock or the tx_coreclock.  Beginning in Quartus® II version 5.1, the default setting is tx_coreclock.  Using tx_coreclock to register the data before it feeds the SERDES is the better choice since it will have the optimal phase position to register the data with respect to the high speed clock that drives the SERDES. 

Your setup timing violations should be eliminated when using tx_coreclock instead of tx_inclock to register the data in the altlvds_tx function.  Additionally, you should see better timing margins when using tx_coreclock instead of tx_inclock even if you do not have timing violations.

Related Products

This article applies to 1 products

Stratix® II FPGAs

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