Article ID: 000080992 Content Type: Troubleshooting Last Reviewed: 01/06/2017

Why doesn't my HPS JTAG work, but my FPGA JTAG works?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The FPGA JTAG does not require an external clock source other than TCK clock. However the HPS JTAG requires an external clock source derived from the EOSC1 pin.  The Debug Access Port (DAP)  uses the dbg_clk generated from the clock when controlling the HPS JTAG. 

Resolution

To resolve this issue ensure the EOSC1 pin  has an external clock source,  and set the clock manager to supply the dbg_clk to the DAP.

Related Products

This article applies to 5 products

Arria® V ST SoC FPGA
Cyclone® V SE SoC FPGA
Cyclone® V ST SoC FPGA
Cyclone® V SX SoC FPGA
Arria® V SX SoC FPGA

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