Article ID: 000080982 Content Type: Troubleshooting Last Reviewed: 11/03/2016

Why does the DisplayPort example design not show the output video?

Environment

    Quartus® II Subscription Edition
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Description

When you use the DisplayPort (DP) example designs available in the Quartus® Prime software v15.1 Update 2 or earlier, the hardware demo designs may fail to display the video. This problem can occur even when the link is successfully trained, if the DP color depth setting is incompatible with the color depth supported by the monitor.

Resolution

Verify the color depth setting in the example design is compatible with the monitor color depth.

Altera® recommends that you use the same color depth setting as the monitor supports.

If needed, adjust the following color depth parameters according to the monitor color depth.

For example, if the design needs to work with 10 bit per color(bpc) (or 30 bit per pixel) monitor as well as 24 bit pixel monitor, set the color depth parameters to 10 bpc (or 30 bpp) as follows:

   - Set DP Source maximum video input color depth to 10 bpc

   - Set DP Sink maximum video output color depth to 10 bpc

   - Set Bitec pixel clock recovery bitec_clkrec_i.BPP to 30

In addition, enable all color depth  support options in the DP parameter editor that may be supported by the maximum video color depth.

Below are the steps for adjusting the color depth setting in the example design:

  a. In Quartus, click 'File --> Open' and select 'control.qsys'

  b. Click on DisplayPort component(dp) in Qsys, set the maximum video input/output color depth to 10 bpc for DP Source and Sink in the parameter editor GUI

  c. Turn on all Source and Sink color depth support options supported by the maximum 10 bpc:

         - 6-bpc RGB or YCbCr 444 (18 bpp)

         - 8-bpc RGB or YCbCr 444 (24 bpp)

         - 10-bpc RGB or YCbCr 444 (30 bpp)

         - 8-bpc YCbCr 422 (16 bpp)

         - 10-bpc YCbCr 422 (20 bpp)

  d. Save the Qsys system and Generate HDL 

  e. In the top level module(e.g. a10_dp_demo.v), set the pixel clock recovery module (bitec_clkrec) BPP parameter to 30

  f. Compile the project

  g. Download .sof file. If needed, reset the FPGA by pressing the reset push button in the FPGA development board.  

In Quartus 16.0 and later, the default color depth in the example design is set to 10 bpc (or 30 bits per pixel). The default setting works with 24-bit pixel monitor as well.

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