Article ID: 000080969 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why does PCIe LTSSM enter Polling.Compliance (0x3) instead of L0 (0xF) state?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

PCI® Express LTSSM enters Polling Compliance when one of the following conditions occurs:

1. Test_in[6] is set to one  

2. Incorrect pin assignments on the PCB

   

Related Products

This article applies to 3 products

Stratix® IV GT FPGA
Stratix® IV GX FPGA
Arria® II GX FPGA