Article ID: 000080963 Content Type: Error Messages Last Reviewed: 10/30/2017

warning (19049) the derive_pll_clocks command is not supported in this family

Environment

    Intel® Quartus® Prime Pro Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

This warning may be seen in the Quartus® software 17.0 and later when your Stratix 10 project contains derive_pll_clocks SDC constraint. 

Resolution

To avoid this warning, you can delete this constraint from SDC file. The project using Stratix 10 device can automatically derive pll clocks. 

Related Products

This article applies to 1 products

Intel® Stratix® 10 FPGAs and SoC FPGAs

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