Article ID: 000080951 Content Type: Error Messages Last Reviewed: 05/07/2025

Internal Error: Sub-system: FYGR, File: /quartus/fitter/fygr/fygr_cdr_op.cpp, Line: 2875

Environment

    Intel® Quartus® Prime Standard Edition
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Description

Due to a problem in the Quartus® Prime Standard Edition Software version 19.1 or earlier, you may see this internal error when the I/O standard is assigned to LVDS, but this pin is not connected to the LVDS IP. This problem only occurs in MAX® V CPLD devices.

Resolution

To work around the problem, change the I/O standard from LVDS to another type of I/O standard if the pins are not connected to the LVDS IP.

Related Products

This article applies to 1 products

MAX® V CPLDs

1