Article ID: 000080951 Content Type: Error Messages Last Reviewed: 12/29/2022

Internal Error: Sub-system: FYGR, File: /quartus/fitter/fygr/fygr_cdr_op.cpp, Line: 2875

Environment

  • Intel® Quartus® Prime Standard Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Standard Edition Software version 19.1 or earlier, you may see this internal error when the I/O standard is assigned to LVDS but this pin is not connected to the LVDS IP. This problem only occurs in Max® V devices.

    Resolution

    To work around the problem, change the I/O standard from LVDS to another type of I/O standard if the pin are not connected to LVDS IP .

    Related Products

    This article applies to 1 products

    MAX® V CPLDs

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.