On rare occasions, a problematic code word transition and DQSEN assertion which occur close to the rising edge of DQSIN may create a race condition causing distortion and/or glitch at the DQS delay chain output resulting in random read errors. Check the table below for the use cases affected based on the Quartus® II software version used.:
| Device | Memory Controller Location | Memory Interface Type | Frequency (MHz) | Quartus II Prior to v13.0sp1.dp5 | Quartus II v13.0sp1.dp5 to v14.0.2 | Quartus II v14.1 or later |
| Cyclone® V & Cyclone V SoC | HPS | DDR2 & DDR3 | f <= 400 | Sensitive to DQS Glitch | Not Affected | Not Affected |
| LPDDR2 | f <= 333 | Not Affected | ||||
| FPGA | LPDDR2 | f <= 333 | Not Affected | |||
| DDR2 & DDR3 | f < 250 | Not Affected | ||||
| 250 <= f < =400 | Sensitive to DQS Glitch | |||||
| Arria® V & Arria V SoC | HPS | DDR2 & DDR3 | f < 450 | Sensitive to DQS Glitch | Not Affected | Not Affected |
| f >= 450 | Sensitive to DQS Glitch | |||||
| LPDDR2 | f <= 400 | Not Affected | ||||
| FPGA | LPDDR2 | f <= 333 | Not Affected | |||
| DDR2 & DDR3 | f < 250 | Not Affected | ||||
| f >= 250 | Sensitive to DQS Glitch |
This issue was partially corrected in Quartus II software release version 13.0sp1 and fully resolved in version 14.1 and later, through bypassing the DQS delay chain. Regenerate the EMIF IP and recompile the design with Quartus II version 14.1 or later. For designs using Cyclone V and Cylcone V SOC, and customers who are unable to upgrade to Quartus II version 14.1, please contact Altera using mySupport.
For designs using Arria V devices, refer to the following link:
https://www.altera.com/support/support-resources/knowledge-base/solutions/rd06222015_999.html
Patches for related Quartus II software versions can be obtained from the following links:
Quartus II 13.0SP1:
Quartus II 13.1.4:
Quartus II 14.0.2: