Article ID: 000080932 Content Type: Troubleshooting Last Reviewed: 09/23/2011

Fixed timing simulation of Stratix IV SERDES_RX

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    A bug in timing simulation of Stratix IV SERDES_RX was fixed, and, as a result, the timing simulation of SERDES_RX does not capture the data bit correctly. This issue does not affect silicon behavior.

    Resolution

    No workaround.

    Related Products

    This article applies to 1 products

    Stratix® IV FPGAs

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