9.8G CPRI IP Core Variations That Target an Arria V GZ Device Do Not Achieve Timing Closure

CPRI IP core variations with a CPRI line rate of 9.8 Gbps that target an Arria V GZ device fail to achieve timing closure with the default Quartus II Fitter settings. Specifically, they experience hold time violations on the PCS-PLD path and setup time violations on the PLD-PCS path.

To achieve better timing closure results, perform the following actions:

• To avoid the hold time violations on the PCS-PLD path, turn off register packing along this path in the Quartus II Fitter settings, by adding the following assignments:

set_instance_assignment -name AUTO_PACKED_REGISTERS_STRATIXII OFF -to *gen_cpri_rx*buf_wr_data*

set_instance_assignment -name AUTO_PACKED_REGISTERS_STRATIXII OFF -to *gen_phy_loop*buf_wr_data*

• To avoid the setup time violations on the PLD-PCS path, add set_max_delay assignments to overconstrain timing.

This issue will be fixed in a future version of the CPRI MegaCore function.