Article ID: 000080889 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why does the MegaWizard-generated variation for my true dual-port memory give lower-than-expected performance?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

There is a problem in the MegaWizard™ Plug-in Manager in the Quartus® II software version 9.1, 9.1 SP1 and 9.1 SP2, that generates variation files with incorrect settings for true dual-port memories. This problem results in fMAX performance that is lower than expected. This problem affects Arria® II GX, Cyclone® III, HardCopy® III, Stratix® III and newer devices and occurs on true dual-port memories that display new data for same-port read-during-write access and do not use byte-enable.

To work around this problem, perform the following steps:

  1. Use the MegaWizard Plug-In to open the variation file for your true dual-port memory.
  2. Proceed to the Output2 page.
  3. Change the Port A Read-During-Write Option to Old Data and back to New Data.
  4. Verify that the option Get x's for write masked bytes instead of old data when byte enable is used is turned on even though the option is disabled (gray).
  5. Repeat steps 3 and 4 for Port B Read-During-Write Option.
  6. Click Finish and generate the output files for your variation.

If you go back to any previous pages after making these changes on the Output2 page, the parameters may return to the incorrect values, and you may have to reapply these changes, even if you do not make any changes on the previous pages.

This problem is scheduled to be fixed in a future version of the Quartus II software.

Related Products

This article applies to 12 products

Stratix® IV GX FPGA
Arria® II GX FPGA
Cyclone® III FPGAs
Cyclone® III LS FPGA
Cyclone® IV E FPGA
Cyclone® IV GX FPGA
HardCopy™ III ASIC Devices
HardCopy™ IV E ASIC Devices
HardCopy™ IV GX ASIC Devices
Stratix® III FPGAs
Stratix® IV E FPGA
Stratix® IV GT FPGA

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