Article ID: 000080886 Content Type: Troubleshooting Last Reviewed: 08/18/2012

Limitations in Support for 400MHz DDR3 Hard Memory Controller With MPFE Interfaces Targeting Cyclone V Devices


  • Quartus® II Subscription Edition

    Critical Issue


    This problem affects DDR3 products.

    The following limitations exist in support for 400MHz DDR3 hard memory interfaces with multiport front end, targeting Cyclone V devices:

    Issue 1:

    Hardware test using the example design might fail even if there is no timing violation reported in TimeQuest.

    Issue 2:

    Avalon data widths greater than 64 bits are not supported.

    Issue 3:

    Correct operation of the unidirectional Avalon port has not been verified.


    The following workarounds apply to these issues:

    Issue 1:

    Setup and hold timing margin for transfers between hard memory controller and core logic might not be balanced. Use set_min_delay constraint to increase the hold time margin for transfers between the hard memory controller and the core logic.

    This issue will be fixed in a future version.

    Issue 2:

    Use Avalon data widths of 32 bits or 64 bits.

    Data widths of 128 and 256 bits will be supported in a future version.

    Issue 3:

    There is no workaround for this issue.

    Operation of the unidirectional Avalon ports will be verified in a future version.

    Related Products

    This article applies to 1 products

    Cyclone® V FPGAs and SoC FPGAs



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