Article ID: 000080882 Content Type: Troubleshooting Last Reviewed: 05/21/2013

Triple Speed Ethernet Recovery Timing Failure

Environment

  • Arria® V FPGAs and SoC FPGAs
  • Quartus® II Subscription Edition
  • Ethernet
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    The Triple Speed Ethernet MegaCore function may have recovery timing violation. The failing path contains a global clock signal driven from the FPGA core logic.

    The recovery timing violation may impact your design in hardware during reset condition.

    This issue affects all designs using Arria V devices in version 13.0 of the Triple Speed Ethernet MegaCore function.

    Resolution

    You need to constrain the signal in the Quartus II software fitter from using a global clock (GCLK). Refer to the Quartus II software compilation report to find the right path for the affected reset path. For example, if the signal with the timing violation is the global reset altera_tse_reset_synhronizer_chain_out, use the following Quartus II software assignment to force the signal to not use a GCLK:

    set_instance_assignment- name GLOBAL_SIGNAL OFF - to altera_tse_ps_pma:altera_tse_pcs_pma_instlaltera_tse_top_1000_base_x:altera_tse_top_1000_base_x_instlaltera_tse_reset_synchronizer:reset_sync_0laltera_tse_reset_synchronizer_chain_out

    This issue will be fixed in a future version of the Triple Speed Ethernet MegaCore function.

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.