Article ID: 000080880 Content Type: Troubleshooting Last Reviewed: 09/11/2012

If you do not use the ALTCLKCTRL megafunction, how does Quartus II v4.0 (and newer) allocate the Stratix II dedicated clock network resources (global, regional, or dual regional clock networks)?


Description If you choose not to use the ALTCLKCTRL megafunction, the Stratix dedicated clock network resources are allocated based on the following priorities: 1. First the user global assignments are honored. The QSF file GLOBAL_SIGNAL variable specifies the type of global assignment (global, regional or fast regional). If the ALTCLKCTRL megafunction is used, the type of global assignment can be AUTO, in which case Quartus II will decide the type of global assignment. 2. Next the PLL clock outputs are placed on clock networks. The global clock network is preferred, unless the PLL uses more than four clock outputs. If the PLL uses four clock outputs, the regional or dual-regional clock networks are used, and are chosen based on the clock fan-out. 3. If requirements 1 and 2 are filled and there are global clock networks left, Quartus II will pick signals based on the following order. a. Any clock signals. The default GLOBAL_SIGNAL option is on. b. Any asynchronous clear signals. The default GLOBAL_SIGNAL option is on. c. Any Read Enable, Write Enable signals. The default GLOBAL_SIGNAL option is off. If there is a no fit because of a lack of global clock networks, you have to make assignments to use regional or dual-regional clock networks.

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Stratix® II FPGAs



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