Article ID: 000080876 Content Type: Troubleshooting Last Reviewed: 03/19/2014

Why is timing not closing in my Stratix V Hard IP for PCI Express on Quartus 13.1?

Environment

    Quartus® II Subscription Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description Timing may not closing in the Stratix® V Hard IP for PCI® Express because constraints are missing on internal clocks that are in separate domains.
Resolution

The missing constraints can be added to your top level Synopsis Design Constraint (sdc) file as below:

set_false_path -from [get_clocks {reconfig_xcvr_clk}]  -to [get_clocks {*|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|coreclkout}]
set_false_path -from [get_clocks {*|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|coreclkout}]  -to  [get_clocks {reconfig_xcvr_clk}]

Related Products

This article applies to 3 products

Stratix® V GX FPGA
Stratix® V GT FPGA
Stratix® V GS FPGA

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