Article ID: 000080871 Content Type: Troubleshooting Last Reviewed: 12/13/2019

Why does the Intel® Arria® 10/Cyclone® 10 Hard IP for PCI Express* with Avalon® Memory Mapped (Avalon-MM) DMA interface generated example design encounter fatal error in simulation?

Environment

  • Intel® Cyclone® 10 GX FPGA
  • Intel® Arria® 10 GT FPGA
  • Intel® Arria® 10 GX FPGA
  • Intel® Arria® 10 SX SoC FPGA
  • Intel® Quartus® Prime Pro Edition
  • Intel® Quartus® Prime Standard Edition
  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
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    Description

    Due to a problem with the Intel® Quartus® Prime software version 19.3 and earlier, you may encounter the above problem when simulating the example design generated from the Intel® Arria® 10/Cyclone® 10 Hard IP for PCI Express* with Avalon® Memory Mapped (Avalon-MM) DMA interface and Gen2 mode in Modelsim* Intel® FPGA Starter Edition.   

    Resolution

    This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition software version 19.4.

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