Article ID: 000080867 Content Type: Troubleshooting Last Reviewed: 07/08/2019

When using the E-tile Hard IP for Ethernet Intel® FPGA IP in 100GE or 1 to 4 10GE/25GE with optional RSFEC and 1588 PTP core variant with PTP enabled, why does the fitter fail if using the EHIP 1/3 IEEE1588/PTP channel placement restriction?

Environment

  • Intel® Agilex™ FPGAs and SoC FPGAs
  • Intel® Stratix® 10 MX FPGA
  • Intel® Stratix® 10 TX FPGA
  • Intel® Quartus® Prime Pro Edition
  • E-tile Hard IP for Ethernet Intel® FPGA IP
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    Critical Issue

    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition version 19.1 software,  the E-tile Hard IP for Ethernet Intel® FPGA IP in 100GE or 1 to 4 10GE/25GE with optional RSFEC and 1588 PTP core variant with PTP enabled cannot pass fitter compilation if using EHIP 1/3 as the channel placement restriction.

    Resolution

    To work around this error, use EHIP 0/2 instead of EHIP 1/3 as the channel placement restriction.

    This problem has been fixed starting in v19.2 of the Intel® Quartus® Prime Pro Edition software.

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