Article ID: 000080861 Content Type: Troubleshooting Last Reviewed: 01/23/2020

Why the ECC error flag incorrectly asserted in the Triple-Speed Ethernet Intel® FPGA IP?

Environment

  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Arria® V GZ FPGA
  • Stratix® V FPGAs
  • Intel® Quartus® Prime Standard Edition
  • Intel® Quartus® Prime Pro Edition
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    Critical Issue

    Description

    Due to a problem in the Intel® Quartus® Prime Software version 18.1 and earlier, the mac_eccstatus signal of the the Triple-Speed Ethernet Intel® FPGA IP core incorrectly flags both correctable and uncorrectable errors when the ECC protection feature is enabled.

    Resolution

    No work around to this problem exists.

    This problem has been fixed in the Intel® Quartus® Prime Software version 19.1 or later.

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