Article ID: 000080860 Content Type: Troubleshooting Last Reviewed: 10/22/2019

Why does the 25G Ethernet Intel® FPGA IP core Design Example with IEEE 1588v2 feature enabled halt in Xcelium* and NCSim* Simulators?

Environment

    Intel® Quartus® Prime Pro Edition
    25G Ethernet Intel® FPGA IP
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Critical Issue

Description

Due to a problem in the Intel® Quartus® Prime Pro Edition software version 19.2, you may see the 25G Ethernet Intel® FPGA IP core design example with IEEE 1588v2 feature enabled halt in Xcelium* and NCSim* Simulators.

Resolution

 To work around this problem when using Intel® Quartus® Prime Pro Edition v19.2 software, use other simulators available in the example design, such as Mentor* ModelSIM* or Synopsys* VCS* simulators. 

This problem is fixed starting from Intel® Quartus® Prime Pro Edition v20.3 software onwards.

Related Products

This article applies to 2 products

Intel® Arria® 10 FPGAs and SoC FPGAs
Intel® Stratix® 10 FPGAs and SoC FPGAs

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