Article ID: 000080856 Content Type: Troubleshooting Last Reviewed: 11/06/2019

Why does the Intel® Stratix® 10 PCIe* Avalon® -MM Hard IP fail to respond to inbound memory read TLPs with the No Snoop bit set?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a limitation of the Intel® Stratix® 10 PCIe* Avalon® -MM Bridge, inbound memory read TLPs with the No Snoop bit set will be dropped and no completions returned, which can cause system failure.

    Resolution

    To work around this problem, constrain the link partner to only send the Memory read TLPs without the No Snoop bit set to the Intel® Stratix® 10 PCIe* Avalon® -MM Hard IP.

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