Article ID: 000080855 Content Type: Troubleshooting Last Reviewed: 01/23/2020

Why is the Control Status Register(CSR) latency inconsistent during back-to-back interleaved reads between TX and RX statistics counter in the Triple-Speed Ethernet Intel® FPGA IP operating in 10Mbps speed mode?

Environment

    Intel® Quartus® Prime Pro Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

Due to a problem in the Intel® Quartus® Prime Software version 19.1 and 19.2, inconsistent CSR latency will be observed during back-to-back interleaved reads between TX and RX statistics counters in the Triple-Speed Ethernet Intel® FPGA IP operating in 10Mbps speed mode.

Resolution

To work around this problem, add interval of more than 1300ns between any Tx path statistics counter read to Rx path statistics counter read.

 

This problem has been fixed starting in the Intel® Quartus® Prime Pro Software version 19.3.

Related Products

This article applies to 3 products

Intel® Cyclone® 10 GX FPGA
Intel® Arria® 10 FPGAs and SoC FPGAs
Intel® Stratix® 10 FPGAs and SoC FPGAs

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.