Article ID: 000080852 Content Type: Troubleshooting Last Reviewed: 09/24/2019

Why does the example design simulation in NCSim® or Xcelium® fail for the Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Core variant when selecting the “Enable RS-FEC” or “Enable Dynamic RS-FEC” options?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Low Latency 100G Ethernet Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem in the Intel® Quartus® Prime Pro software version 18.1 and earlier, the example design’s simulation for the Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Core variant with the “Enable RS-FEC” or
    “Enable Dynamic RS-FEC” options selected will fail in NCSim® or Xcelium®. This failure will typically take the form:

    *F,NOSNAP: Snapshot 'basic_avl_tb_top' does not exist in the libraries.

    Resolution

    To work around this issue, do not select either the “Enable RS-FEC” or “Enable Dynamic RS-FEC” options in the IP’s GUI editor when generating the example design for simulation in NCSim or Xcelium.

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro software.

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