Why does the example design simulation in NCSim® or Xcelium® fail for the Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Core variant when selecting the “Enable RS-FEC” or “Enable Dynamic RS-FEC” options?

Due to a problem in the Intel® Quartus® Prime Pro software version 18.1 and earlier, the example design’s simulation for the Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP Core variant with the “Enable RS-FEC” or
“Enable Dynamic RS-FEC” options selected will fail in NCSim® or Xcelium®. This failure will typically take the form:

*F,NOSNAP: Snapshot 'basic_avl_tb_top' does not exist in the libraries.

To work around this issue, do not select either the “Enable RS-FEC” or “Enable Dynamic RS-FEC” options in the IP’s GUI editor when generating the example design for simulation in NCSim or Xcelium.

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro software.