Article ID: 000080849 Content Type: Troubleshooting Last Reviewed: 05/05/2021

Why is there an unconstrained clock reported when using the Dual Configuration Intel® FPGA IP on Intel® MAX® 10?

Environment

  • Intel® Quartus® Prime Standard Edition
  • Dual Configuration Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    An unconstrained clock is reported as shown below when using Dual Configuration Intel® FPGA IP on MAX®10:

    altera_dual_boot:dual_boot_0|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|ru_clk

     

     

    Resolution

    To work around this problem, generate timing constraints including the command "create_generated_clock" in the SDC file. 

    Related Products

    This article applies to 1 products

    Intel® MAX® 10 FPGAs

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