Article ID: 000080848 Content Type: Error Messages Last Reviewed: 12/29/2022

Critical Warning(16643): Found INPUT_TERMINATION assignments found for "ref_clk" pin with multiple values. Using value: "OFF"

Environment

    Intel® Quartus® Prime Pro Edition
    Triple-Speed Ethernet Intel® FPGA IP
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Description

Due to a problem with the Intel® Quartus® Prime Pro version 19.1, you may encounter the above critical warning when using the Triple-Speed Ethernet Intel® FPGA IP with LVDS I/O design when the default input termination
of LVDS reference clock is overridden by using the following QSF assignment or through the assignment editor.

set_instance_assignment -name INPUT_TERMINATION OFF -to ref_clk

Resolution

To work around this problem, remove the following line from the QIP file of the Triple-Speed Ethernet Intel® FPGA IP when there is a need to override the default input termination of the LVDS reference clock setting.

set_instance_assignment -entity "" -library "altera_lvds_core14_191" -name INPUT_TERMINATION DIFFERENTIAL -to inclock

Related Products

This article applies to 10 products

Intel® Stratix® 10 SX SoC FPGA
Intel® Stratix® 10 DX FPGA
Intel® Arria® 10 SX SoC FPGA
Intel® Stratix® 10 GX FPGA
Intel® Cyclone® 10 GX FPGA
Intel® Arria® 10 GT FPGA
Intel® Cyclone® 10 LP FPGA
Intel® Arria® 10 GX FPGA
Intel® Stratix® 10 MX FPGA
Intel® Stratix® 10 TX FPGA

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