Article ID: 000080846 Content Type: Product Information & Documentation Last Reviewed: 03/18/2019

How do I enable the DisplayPort® IP to support the Adaptive Sync feature for Intel® Arria® 10 Device and Intel® Cyclone® 10 Device?

Environment

  • Intel® Quartus® Prime Pro Edition
  • DisplayPort Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The Intel® DisplayPort® IP supports the Adaptive Sync feature when using the Intel® Quartus® Prime Pro Edition. The Adaptive Sync feature is demonstrated through the DisplayPort® SST Parallel Loopback Design Example. However, there is no description to enable this feature in the Intel® FPGA DisplayPort® Design Example User Guide for Intel® Arria® 10 Device (release of 06-Nov 2017) and Intel® Cyclone® 10 Device (release of 25-Dec 2017).

    Resolution

    To enable support for the adaptive sync feature in the design example, you need to edit the MSA_TIMING_PAR_IGNORED bit of the DPCD 00007h register and the MSA_TIMING_PAR_IGNORE_EN bit of the DPCD 00107h register in the rx_utils.c file in the software folder.

     

    Note: The adaptive sync feature is applicable only when you turn on the Enable GPU control parameter.

          To edit the bits:

          1. Locate data[7] = 0x80; //DPCD_ADDR_DOWN_STREAM_PORT_COUNT.

          2. Change 0x80 to 0xC0.

          3. Locate data[7] = 0x00; //DPCD_ADDR_DOWNSPREAD_CTRL

          4. Change 0x00 to 0x80.

          5. Regenerate the ELF file.

          6. After programming the SOF file into FPGA, program the updated ELF file into FPGA.

         

    This information is scheduled to be added in a future release of the Intel® FPGA DisplayPort® Design Example User Guide for Intel® Arria® 10 and Intel® Cyclone® 10 Devices.

    Related Products

    This article applies to 2 products

    Intel® Cyclone® 10 FPGAs
    Intel® Arria® 10 FPGAs and SoC FPGAs

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