Article ID: 000080836 Content Type: Troubleshooting Last Reviewed: 05/05/2021

Why does the Intel® Stratix® 10 PCI Express* Avalon®-MM Hard IP with External descriptor controller example design hang when more than 8 descriptors are programmed?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to incorrect address mapping of the router logic generated by the Intel® Quartus® Prime Pro Platform Designer tool , the Intel® Stratix® 10 PCIe* Avalon®-MM Hard IP with External descriptor controller example design will hang when more than 8 descriptors are programmed.

    Resolution

     

    To work around this problem, manually correct the RTL files generated by the Intel® Quartus® Prime Pro Platform Designer tool:

     

    1.   Search *altera_merlin_router*.sv under project workspace and find files shown below:

    ../altera_merlin_router_xxx/sim/altera_merlin_router_xxx (simulation flow)

    ../altera_merlin_router_xxx/syn/altera_merlin_router_xxx (implementation flow) 

     

    2.   Open each file to confirm if following lines exist, then modify them accordingly:

    Original lines should be:       

            //-------------------------------------------------------       

            // Figure out the number of bits to mask off for each slave span       

            // during address decoding       

            //-------------------------------------------------------       

            localparam PAD0 = log2ceil(64'h2000 - 64'h0);       

            localparam PAD1 = log2ceil(64'h1000100 - 64'h1000000);       

            localparam PAD2 =log2ceil(64'h1002100 - 64'h1002000);

    Change to:       

            //-------------------------------------------------------       

            // Figure out the number of bits to mask off for each slave span       

            // during address decoding       

            //-------------------------------------------------------       

            localparam PAD0 = log2ceil(64'h2000 - 64'h0);       

            localparam PAD1 = log2ceil(64'h1001000 - 64'h1000000);   

            localparam PAD2 = log2ceil(64'h1003000 - 64'h1002000);

     

    3.     Run the simulation or compilation flow again.

     

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition software.

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