Article ID: 000080832 Content Type: Troubleshooting Last Reviewed: 06/19/2019

Why does the Intel® Arria® 10 Hard IP for PCI* Express signal tx_out periodically transition to high impedance in simulation at LTSSM = Recovery Speed state?

Environment

  • Quartus® II Subscription Edition
  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    When the LTSSM is in Recovery Speed state, the Intel® Arria® 10 Hard IP for PCI* Express will send out Electrical Idle Ordered Sets (EIOS) before transitioning to electrical idle. This behavior is represented in simulation by tx_out signal periodically transitioning to high impedance.  Therefore, if a third-party Bus Functionality Model (BFM) used for simulation interprets the high impedance as unknown symbols, this will cause the bit sequence to be corrupted and LTSSM transitioning between Recovery Speed and Recovery Lock state.

    Resolution

    Simulations using Intel® BFM and Avery* BFM are not affected by this behavior.

    If using third party BFM for simulation, please ensure tx_out transitioning to high impedance is not interpreted as unknown symbol.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.