Article ID: 000080830 Content Type: Troubleshooting Last Reviewed: 01/30/2019

Why does the Intel® Stratix® 10 Avalon®-ST PCI Express* Hard IP for H-Tile devices with Multifunction enabled generate RTL with max_read_req_size parameter for PF2 and PF3 set to 0?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
  • PCI Express
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    Critical Issue

    Description

    Due to a problem with the Intel® Quartus® Prime Pro version 18.0, the Intel® Stratix® 10 Avalon®-ST PCI Express* Hard IP for H-Tile devices with Multifunction enabled generates RTL with the max_read_req_size parameter for PF2 and PF3 set to 0 instead of 2 as specified by PCIe* specification.

    Resolution

    This problem is fixed in Intel® Quartus® Prime Pro version 18.1.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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