Article ID: 000080829 Content Type: Troubleshooting Last Reviewed: 05/13/2019

Does the Intel® Arria® 10 and the Intel® Cyclone® 10 GX PCIe* Hard IP support changing the BAR size at run-time before enumeration?

Environment

  • Intel® Cyclone® 10 GX FPGA
  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
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    Description

    The Intel® Arria® 10 and the Intel® Cyclone® 10 GX PCIe* Hard IP does not support changing the BAR size at run-time before enumeration. The BAR Size Mask can only be set during IP GUI configuration and HDL generation.

    Resolution

    Not applicable.

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