Article ID: 000080827 Content Type: Troubleshooting Last Reviewed: 01/28/2019

Why does the Avalon-MM Intel® Stratix® 10 Hard IP for PCI* Express IP's dynamically  generated example design fail timing on Intel® Stratix® 10 ES1 and ES2 devices?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem with the Intel® Quartus® Prime Pro version 18.0 and 18.1, the Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express IP's dynamic generated example design fails static timing analysis.

    Resolution

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime software.

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.