Article ID: 000080825 Content Type: Troubleshooting Last Reviewed: 02/08/2017

Why does the Low Latency 40-100 Gbps Ethernet IP core hang or send erroneous packets for certain TX Avalon-ST interface conditions?

Environment

  • Stratix® V E FPGA
  • Stratix® V GS FPGA
  • Stratix® V GX FPGA