Description
Due to a problem in the Intel® Quartus® Prime Standard Edition software version 18.0 and earlier, the RAM: 1-PORT IP allows you to specify memory initialization file during IP generation. This is not supported for Max® II and Max® V CPLDs. You will see this warning message during synthesis if you have specified the memory initialization file to a RAM: 1-PORT IP. You will also see a different simulation result for RTL vs Gate Level simulation where RTL simulation is incorrect.
Resolution
To work around this problem, select “No, leave it blank” in the Mem Init tab
This problem is fixed beginning with the Intel Quartus Prime Standard Edition software version 18.1