CPRI IP Core Demonstration Testbench Does Not Support Cadence NCSIM Simulator

The CPRI IP core demonstration testbench cannot simulate successfully with the Cadence NCSIM simulator.

Two options are available to you to work around this issue.

You can simulate the CPRI demonstration testbench with the Mentor Graphics ModelSim simulator or the Synopsys VCS MX simulator.

Alternatively, you can edit your testbench files to remove dynamic array declarations of empty arrays. The following changes ensure that your IP core files are compatible with the Cadence NCSIM simulator:

1. Change directory to <instance>_testbench/altera_cpri/cpri_testbench/models/cpri_api.
2. Open the file aux_api.sv in a text editor and replace the following existing line with the following new code:

Replace this existing line:

initial ("../models/cpri_api/aux_data.txt",mem_aux);

with this replacement code:

initial

begin

mem_aux = new[10]; // Use for checking purposes

("../models/cpri_api/aux_data.txt",mem_aux);

end

3. Open the file cpu_api.sv in a text editor and replace the following existing line with the following new code:

Replace this existing line:

initial ("../models/cpri_api/hdlc_data.txt",mem_hdlc);

with this replacement code:

initial

begin

mem_hdlc = new[10]; // Use for checking purposes

("../models/cpri_api/hdlc_data.txt",mem_hdlc);

end

4. Open the file mii_api.sv in a text editor and replace the following existing line with the following new code:

Replace this existing line:

initial ("../models/cpri_api/mii_data.txt",mem_mii);

with this replacement code:

initial

begin

mem_hdlc = new[10]; // Use for checking purposes

("../models/cpri_api/mii_data.txt",mem_mii);

end

5. Change directory to <instance>_testbench/altera_cpri/cpri_testbench.
6. Open the file tb.sv in a text editor and conditionally replace the following existing code with the following new code:

Remove this existing code

initial ("../models/cpri_api/aux_data.txt",mem_aux);

initial ("../models/cpri_api/hdlc_data.txt",mem_hdlc);

initial ("../models/cpri_api/mii_data.txt",mem_mii);

and replace it with this new code, depending on the features

initial

begin

mem_aux = new[10]; // AUX interface is available by default

("../models/cpri_api/aux_data.txt",mem_aux);

// You need include the following two lines only if the DUT includes an HDLC block and you are modifying the testbench to program the DUT for HDLC communication:

mem_hdlc = new[10];

("../models/cpri_api/hdlc_data.txt",mem_hdlc);

// Include the following two lines only if the DUT has an MI interface:

mem_mii = new[10];

("../models/cpri_api/mii_data.txt",mem_mii);

end

This issue is fixed in version 14.0 of the CPRI MegaCore function.