Article ID: 000080760 Content Type: Troubleshooting Last Reviewed: 01/28/2015

When using DPA in Altera devices, is the phase setting fixed after the DPA lock signal is asserted?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

No, in Altera® devices the DPA circuitry keeps adjusting the phase setting unless the optional rx_dpll_hold port in the altlvds megafunction is asserted.

The rx_dpll_hold input port is useful when you know you will have a long period of static data, beyond the DPA run length specification.  You can assert this port to hold the DPA on its current setting.  The DPA lock signal may still toggle, it is not affected by the rx_dpll_hold port. 

When the phase relationship between data and clock changes, the DPA will adjust the phase setting accordingly. The DPA is designed to maintain the optimal phase relationship between the reference clock and data across voltage and temperature variations during device operation. 

Related Products

This article applies to 6 products

Arria® GX FPGA
Stratix® II GX FPGA
Stratix® II FPGAs
Stratix® IV GX FPGA
Stratix® III FPGAs
Stratix® IV E FPGA

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.