Article ID: 000080758 Content Type: Troubleshooting Last Reviewed: 02/20/2014

Low Latency 40-100GbE IP Core VHDL Model Cannot Simulate Correctly

Environment

  • Quartus® II Subscription Edition
  • Simulation
  • Ethernet
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    If you generate a VHDL model for a Low Latency 40-100GbE IP core, it cannot simulate correctly.

    Resolution

    This issue has no workaround. You must generate your IP core variation in Verilog HDL.

    This issue will be fixed in a future version of the Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore function.

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