Article ID: 000080758 Content Type: Troubleshooting Last Reviewed: 02/20/2014

Low Latency 40-100GbE IP Core VHDL Model Cannot Simulate Correctly

Environment

Quartus Edition

Quartus® II Subscription Edition

Version Found: 13.1a10

FPGA Intellectual Property

Simulation

Ethernet

Version Found: 13.1a10

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Critical Issue

Description

If you generate a VHDL model for a Low Latency 40-100GbE IP core, it cannot simulate correctly.

Resolution

This issue has no workaround. You must generate your IP core variation in Verilog HDL.

This issue will be fixed in a future version of the Low Latency 40- and 100-Gbps Ethernet MAC and PHY MegaCore function.

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