Article ID: 000080733 Content Type: Troubleshooting Last Reviewed: 07/04/2016

Timing Violation for Arria 10 DisplayPort Design

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    When you run the DisplayPort design for Arria 10 devices, the design may encounter timing violation on the rx_restart signal. This signal is clocked as rx_std_clkout in the DisplayPort IP core, but connects to the reset pin in the reset controller running on the Avalon Memory-Mapped (Avalon-MM) clock domain.

    Resolution

    To work around this issue, add a reset synchronizer for the rx_restart signal at the top level before you connect to the reset controller.

    This issue is fixed in version 15.1 Update 1 of the DisplayPort IP core.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs

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