Article ID: 000080724 Content Type: Troubleshooting Last Reviewed: 05/10/2013

IP Compiler for PCI Express npor Input Signal is Not Gated by the gxb_powerdown and pll_powerdown Signals in the DMA Chaining Example

Environment

  • Quartus® II Subscription Edition
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    Critical Issue

    Description

    The npor input signal to the IP Compiler for PCI Express must be gated by the gxb_powerdown and pll_powerdown signals, to avoid bringing the hard IP out of reset while offset cancellation is in progress. However, in the generated _plus.v file, the npor signal is not gated as required. As a result, in the chaining DMA example, the npor signal can be asserted while offset cancellation is still in progress.

    Resolution

    To avoid bringing the hard IP out of reset while offset cancellation is in progress, add user logic to gate the npor signal with the gxb_powerdown and pll_powerdown signals.

    This issue will be fixed in a future version of the IP Compiler for PCI Express chaining DMA example.

    Related Products

    This article applies to 1 products

    Cyclone® IV FPGAs

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