Article ID: 000080722 Content Type: Troubleshooting Last Reviewed: 10/17/2011

Fitter fails to place PLLs and errors occur when the zero delay buffer operation mode is used for Stratix V

Environment

  • Quartus® II Subscription Edition
  • PLL
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    If you use the zero delay buffer operation mode, the Fitter can't place PLLs and generates messages similar to the following:

    Error: Could not place pin <pin name>.

    Resolution

    Manually place the external clock output node with a location assignment. The location depends on the PLL location and the target device.

    Related Products

    This article applies to 1 products

    Stratix® V FPGAs

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