Article ID: 000080701 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why do I get a clock skew or setup and hold violation message when my design includes the ALTUFM_SPI megafunction?



Compiling a MAX® II design that accesses user flash memory (UFM) with a serial peripheral interface using the ALTUFM_SPI megafunction results in the following warning message in the Quartus® II software version 5.0 if you do not have a clock setting defined for the ALTUFM_SPI clock signal: Warning: Circuit may not operate. Detected 23 non-operational path(s) clocked by clock "sck" with clock skew larger than data delay.

Such a design results in the following message if you do have a clock setting defined for the ALTUFM_SPI clock signal:

Warning: Can't achieve minimum setup and hold requirements <clock feeding sck port> along 11 paths.

The message is due to an incorrectly calculated clock hold check between LE registers in the megafunction and the UFM data output register. The UFM register has a longer hold time requirement than the hold time of the source LE registers. The ALTUFM_SPI megafunction uses opposite clock edges for the source and destination registers to ensure setup and hold times are met. The warning message appears because the Quartus II Timing Analyzer uses consecutive rising clock edges by default, and the software calculates hold times with no information about the dual-edge clocking within the ALTUFM_SPI megafunction. This issue does not affect the interface operation, and you safely ignore this warning message.

Make the following timing assignments to eliminate messages related to this problem:

  1. Create a clock setting for the SCK clock port and specify an FMAX requirement of 8 MHz or less.
  2. On the UFM data register, make the following assignment:
    1. On the Assignments menu, choose the Assignment Editor:
    2. Create an Inverted Clock assignment with a value of ON for the UFM register (the typical post-synthesis name ends with maxii_ufm_block1_drdout).

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