CPRI IP Core Verilog HDL Variations That Include a MAP Interface Fail Simulation in the Synopsys VCS MX Simulator

CPRI IP core variations that generate in Verilog HDL and that include a MAP interface fail simulation in the Synopsys VCS MX simulator. This issue occurs because of a duty cycle issue on the antenna-carrier interfaces.

Use a different simulator to simulate these variations, or ensure that your design or testbench latches the RX MAP data (the outgoing data on the antenna-carrier interfaces) on the negative edge of the interface clock rather than on the positive edge.

In the testbench, make the following change to latch on the negative clock edge:

In the <variation_name>_testbench/altera_cpri/tb.vhd file, replace the string

(clk_iq_map’event and clk_iq_map = ’1’)

with the string

(clk_iq_map’event and clk_iq_map=’0’)

This issue will be fixed in a future version of the CPRI MegaCore function.