Article ID: 000080685 Content Type: Troubleshooting Last Reviewed: 11/07/2013

Bootloader Fails to Run with UART0 Disabled

Environment

  • Quartus® II Subscription Edition
  • Intel® SoC FPGA Embedded Development Suite (SoC EDS) Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    In v13.1, even if UART0 is disabled in the HPS component, the preloader generator turns on spl.performance.SERIAL_SUPPORT (UART0 serial I/O support).

    In v13.0, even if UART0 is disabled in the HPS component, the preloader generator turns on both spl.performance.SERIAL_SUPPORT (UART0 serial I/O support) and spl.reset_assert.UART0 (UART0 reset support).

    As a result of these errors in preloader settings, when the preloader passes control to the bootloader, the bootloader might not run correctly. For example, U-boot hangs.

    Resolution

    Depending on whether UART0 is enabled, manually enable or disable the following preloader settings:

    • spl.performance.SERIAL_SUPPORT-UART0 serial I/O support
    • spl.reset_assert.UART0-UART0 reset support

    Related Products

    This article applies to 2 products

    Cyclone® V FPGAs and SoC FPGAs
    Arria® V FPGAs and SoC FPGAs

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