Article ID: 000080682 Content Type: Troubleshooting Last Reviewed: 11/11/2019

Why does the 25G Ethernet Intel® FPGA IP interface not work correctly if two independent 25G Ethernet Intel® FPGA IPs with different parameters are instantiated in one Intel® Stratix® 10 FPGA design?

Environment

  • Intel® Stratix® 10 GX FPGA
  • Intel® Quartus® Prime Pro Edition
  • 25G Ethernet Intel® FPGA IP
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    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition version 18.1 or earlier, when you instantiate two "25G Ethernet Intel® FPGA IPs" with different parameters in one Intel® Stratix®10 FPGA design you will see one 25G Ethernet interface will not work as expected.

    If different parameters or features are enabled in one instance of the IP, but disabled in the other problems can be observed. This is because some source files generated by the IP have the same module name but different parameters, thus the software will overwrite the same module if they are implemented in one design. This results in abnormal behaviour for one of the 25G Ethernet interfaces.

    Resolution

    This problem is fixed beginning with the Intel® Quartus® Prime Pro edition software version 19.3.

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