In rare cases, the Intel® Stratix® 10 25G Ethernet IP core may still receive random erroneous packets when operating in open ended condition, i.e. there is no fiber or QSFP28 module connected.
A workaround for this problem is to edit the SYNOPT_STRICT_SOP parameter in the top level IP wrapper file to 1.
This workaround is only available for designs with Preamble Pass-Through feature disabled.
Locate the 25G Ethernet IP variant wrapper file at /synth/<file_name>.v.
At the instantiation of the version specific 25G Ethernet IP, change the SYNOPT_STRICT_SOP parameter setting from (0) to (1).
Do not regenerate the 25G Ethernet IP core. Compile your design.
Example design IP variant file at /synth/ex_25g.v:
Please note that you may observe junk data on the 64-bit l1_rx_data bus. The l1_rx_valid should be used as an indicator to accept or ignore the data.
This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition software.